In modern industrial equipment, computer controllers are being utilized in greater numbers of applications. The need for electrical isolation between the low voltage of controllers and the high voltage of motors or equipment is growing. Depending on the equipment being controlled, there are various known approaches used to isolate the systems electrically but that still allow electrical coupling. Isolation provides an AC path for signals or power between two circuits but eliminates direct connections. This is important where ground potential differences exist between nodes. Isolation is used to break the direct connection paths between the signal domains and to break the common ground loop, because noise can be transmitted through the ground loop that would otherwise interfere with the proper operation of the circuits. Known isolation approaches can include using a transformer to couple circuits magnetically, an RF signal to couple through a radiated energy, an opto-isolator using light energy, or using a capacitor between the two circuits that couples the circuits using an electric field. Other isolation needs include integration of analog and digital circuitry onto a single packaged integrated circuit with separate power domains, for example.
Although opto-isolators are a suitable solution for low speed communication applications, in other applications where isolation is required and an opto-isolator is not appropriate, a capacitor is needed. Capacitors provided on a circuit board or as part of the package for integrated circuits have been used for isolation, for example, U.S. Pat. No. 4,780,795, entitled “Packages for Hybrid Integrated Circuit High Voltage Isolation Amplifiers and Method of Manufacture,” issued Oct. 25, 1988 to Meinel, discloses a hybrid package for integrated circuits that includes two silicon integrated circuit devices positioned within a package and the use of planar discrete capacitors formed on a ceramic substrate also within the package for isolation between the two silicon circuits. However as integration of circuits onto silicon continues to advance, isolators that can be formed on the semiconductor substrate with other circuitry, e.g., integrated capacitor isolators, are used and desired. To gain increased capacitance values for use with higher voltages, the capacitors used in the prior known approaches can be coupled serially, however, this approach requires additional silicon area. Integrated capacitors of values capable for high voltage isolation are therefore desired. These capacitors could be used serially to gain still higher capacitor values, or the isolation capacitors could be used to form discrete components as well as being used in integrated circuits with additional circuitry.
Within the present application and as currently described in the power circuits industry, low voltage is considered as below 50V, high voltage is defined as a voltage greater than 50 Volts and less than 5,000 volts. Extra-high voltage is a voltage greater than 5,000 Volts and less than about 20,000 Volts. Arrangements herein are directed at high voltage and extra-high voltage applications.
With the trend for miniaturization, control interfaces utilizing integrated capacitors for isolation are needed. Integrated capacitors provide the smallest solution for isolation and power circuit applications. However, in the prior known approach solutions, to create an integrated capacitor in the extra-high voltage range, greater than 5,000 Volts peak for example, the large capacitance needed has been formed by coupling two or more lower voltage capacitors in series. Increased capacitor values are therefore desired to further reduce the silicon area needed to achieve a particular isolation circuit solution.
The breakdown voltage of an ideal parallel plate capacitor is related to the dielectric strength and distance between the plates as shown in Equation 1:Vbd=Edsd   EQUATION 1
Where:    Vbd=breakdown voltage; Eds=dielectric strength and d=distance between plates
Equation 1 illustrates that for a constant dielectric material, increasing the distance between the capacitor plates will linearly increase the breakdown voltage. In an integrated circuit, where two different metal layers may typically form the capacitor plates, the plate distance d is increased by increasing the dielectric thickness between the layers. However, in an integrated circuit process, a dielectric thickness increased to a distance sufficient for high voltage capacitors can also lead to wafer bowing or warpage, and to increase the dielectric thickness enough so that the Vbr is greater than 5,000 volts, the wafer warpage can become so pronounced that semiconductor processing equipment downstream from the dielectric thickening step is not able to properly process the wafers. In addition, in a known approach that uses the typical multiple level metal layer systems with inter-metal dielectrics to achieve a sufficiently thick dielectric for high voltage capacitors, the process of adding multiple layers of metal and oxide, then stripping away the unwanted metal areas so as to create the desired dielectric thickness results in electrical degradation of the capacitor. The additional process operations of forming metal, photoresist, etch, leveling/planarization such as chemical mechanical polishing (CMP) and clean-up cause increased defects and add extra costs to the production of the wafer, which are undesirable. However, in an integrated circuit process, increasing the dielectric thickness to a distance sufficient for high voltage and extra-high voltage capacitors has a number of challenges. Extremely thick layers of generally compressive dielectric films can lead to severe wafer warpage, such that semiconductor processing equipment downstream from the dielectric deposition step is not able to properly process the wafers. In addition, embedding additional metal levels for no reason other than to increase the dielectric thickness between bottom and top plates of the capacitor results in a significant cost increase related to the repeated processing loop of forming inter-level connection vias, then a patterned metal layer, then depositing and planarizing a dielectric material over the metal layer.
Continuing improvements are therefore needed for methods and apparatus to provide integrated high voltage and extra-high voltage value capacitors that can be manufactured using conventional semiconductor processing methods and with known equipment, and at a relatively low cost.